Conventionally, in a digital recording disk device, digital recording VTR etc., data are recorded after converting into a recording code, without recording the data as they are. Therein, 1,7 code and 2,7 code are typical recording codes.
In 1,7 code, after a 2-bit data bit is converted into a 3-bit channel bit or after a 4-bit data bit is converted into a 6-bit channel bit, it is recorded by using NRZI rule. The NRZI rule is a recording rule that inversion is conducted by "1" and non-inversion is conducted by "0". A big characteristic of 1,7 code is that there exists 1 or more and 7 or less of "0" between "1" and "1" after converting, i.e., the minimum inversion interval is 2.
In 2,7 code, after a 2-bit data bit is converted into a 4-bit channel bit or after a 3-bit data bit is converted into a 6-bit channel bit, it is recorded by using the NRZI rule. A big characteristic of 2,7 code is that there exists 2 or more and 7 or less of "0" between "1" and "1" after converting, i.e., the minimum inversion interval is 3.
A method has been suggested where, to record and reproduce signals, the data detection is conducted by combining partial response equalization and Viterbi decoding. For example, this method is disclosed in Japanese patent application laid-open No.4-298865(1992) (application No.3-64201(1991)) titled "Method of Detecting Reproduce Data".
In the reproduce data detection method described in No.4-298865, a code with a minimum inversion interval of 2, such as 1,7 code is recorded. In reproducing, a bit error correction process is conducted by converting a reproduce signal into a ternary data by PR(1,1) equalization and then decoding it by four-state Viterbi decoding to reduce an error rate.
However, in the conventional reproduce data detection method that uses the combination of a partial response equalization system and Viterbi decoding, there is a problem that it cannot conduct a reproduction-adaptive operation, whereas it can perform a bit error correction to reduce the error rate. Namely, PR(1,1) equalization always conducts fixed equalization even when a change in reproduce signal due to a variation in record current when recording, a variation in medium characteristics caused by a record position, a variation in record and reproduce characteristics caused by temperature or the like occurs. Therefore, the equalization characteristic cannot follow the change in reproduce signal.
On the other hand, Japanese patent application laid-open No.6-20208(1994) discloses a non-linear distortion equalization adaptive equalizer where an inter-symbol interference distortion and a non-linear distortion included in read-out output from a high-density magnetic recording device for digital signal can be removed by the smaller amount of operation. The equalizer comprises: an estimate value signal memory to store several estimate signals read out from the combination of equalization address signal and Viterbi transition symbol system signal; a Viterbi decoder which conducts the equalization according to Viterbi algorithm while using, as branchmetric, several error signals to show errors between several estimate signals output from the estimate value signal memory and input data symbols, and outputs a estimate symbol to input data symbol, equalization address signal and correction address signal; and a corrector to renew the estimate value signal to be shown with the correction address signal by the input data symbol.
This non-linear distortion equalization adaptive equalizer can remove an inter-symbol interference distortion and a non-linear distortion included in read-out output from a high-density magnetic recording device for digital signal by the smaller amount of operation, as compared with the conventional Viterbi decoding, and can follow a time-dependent change in non-linear distortion.
However, Japanese patent application laid-open No. 6-20208 does not suggest any application of the non-linear distortion equalization adaptive equalizer to the partial response equalization system.
Further, in the method and equalizer disclosed in Japanese patent application laid-open Nos.4-298865 and 6-20208, input data are serially processed every one clock. Especially, when image signals are recorded, the clock frequency may be more than 100 MHz. Thus, the operation must be very difficult to such a frequency even when the circuit is a LSI.